The present invention relates to comparator circuits and, more particularly, to a comparator circuit including a transconductance reduction input differential stage from which hysteresis is developed to provide a small amount of threshold voltage level change as the comparator switches operating states in response to an applied input signal.
The prior art is replete with comparator circuits having hysteresis for causing the threshold level to change as an applied input signal varies above and below the threshold level. In this manner noise that may be imposed onto the input signal does not cause false switching of the comparator output state as the input signal crosses the threshold level of the comparator.
Although prior art comparators work quite well they are not necessarily suited for use in high density single chip integrated circuits where size is critical. For instance, a microprocessor support chip may require such a comparator for providing logic level conversion between transistor transistor logic (TTL) and RS423 logic levels and vice versa. In order to save die area which may be necessary if the support chip is very complex it is desirable to provide such comparator function in as little area of the integrated circuit (IC) as possible. Prior art circuits may require too much die area for contemporary complex ICs.
Hence, a need exists for an improved comparator circuit having hysteresis which consumes minimal die area.